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MP2107/MP2107A
4A, 6V Synchronous Step-Down Switching Regulator
The Future of Analog IC Technology
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - PHOTOFAST INTERNAL USE ONLY
POK (MP2107)
POK
SW
MP2107 MP2107A
VOUT 1.8V / 4A
EFFICIENCY (%)
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DESCRIPTION FEATURES
The MP2107 is an internally compensated 1.5MHz fixed-frequency PWM synchronous step-down regulator. MP2107 operates from a 2.7V to 6V input and generates an output voltage as low as 0.8V. The MP2107 integrates a 80m high-side switch and a 60m synchronous rectifier for high efficiency without an external Schottky diode. With peak current mode control and internal compensation, the MP2107 based solution delivers a very compact footprint with a minimum component count. The MP2107 is available in a small 3mm x 3mm 10-pin QFN package and the MP2107A is available in an 8-pin SOIC package with an exposed pad. * * * * * * * * * * * * * * 4A Output Current Input Operation Range: 2.7V to 6V 60m Internal Power MOSFET Switches All Ceramic Capacitor Design Up to 95% Efficiency 1.5MHz Fixed Switching Frequency Adjustable Output from 0.8V to 0.9xVIN Internal Soft-Start Frequency Synchronization Input Power Good Output Cycle-by-Cycle Current Limiting Hiccup Short Circuit Protection Thermal Shutdown 3mm x 3mm 10-pin QFN (MP2107) and 8-pin SOIC (MP2107A) Packages P/ASIC/DSP/FPGA Core and I/O Supplies Printers and LCD TVs Network and Telecom Equipment Point of Load Regulators
APPLICATIONS
* * * *
"MPS" and "The Future of Analog IC Technology" are Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN 5V
Efficiency vs Output Current
95 90 85 80 75 70
IN
BS
5V to 1.8V
5V to 3.3V
5V to 2.5V
OFF ON
EN/SYNC GND
FB
0
1 2 3 OUTPUT CURRENT (A)
4
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2009122006580007
MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - PHOTOFAST INTERNAL USE ONLY
PACKAGE REFERENCE
TOP VIEW
FB 1 2 3 4 5 10 9 8 7 6 EN/SYNC GND SW IN
FB 1 2 3 4
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8 7 6 5 EN/SYNC SW SW
TOP VIEW
GND
GND
SW IN
IN
BS
VCC
BS
POK
EXPOSED PAD ON BACKSIDE CONNECT TO GND
EXPOSED PAD ON BACKSIDE CONNECT TO GND
Part Number* MP2107DQ
Package QFN10 (3mm x 3mm)
Temperature
Part Number* MP2107ADN
Package SOIC8E
Temperature
-40C to +85C
-40C to +85C
*
For Tape & Reel, add suffix -Z (e.g. MP2107DQ-Z) For RoHS Compliant Packaging, add suffix -LF (e.g. MP2107DQ-LF-Z)
* For Tape & Reel, add suffix -Z (eg. MP2107ADN-Z)
For RoHS Compliant Packaging, add suffix -LF (eg. MP2107ADN-LF-Z)
ABSOLUTE MAXIMUM RATINGS (1)
Recommended Operating Conditions
(2)
IN to GND ................................... -0.3V to +6.5V SW to GND .......................... -0.3V to VIN + 0.3V ................................-2.5V to VIN+2.5V for <50ns FB, EN/SYNC, POK to GND.......... -0.3V to +6.5V BS to SW .................................... -0.3V to +6.5V Junction Temperature ...............................150C Lead Temperature ....................................260C Storage Temperature...............-65C to +150C
Supply Voltage VIN ............................. 2.7V to 6V Output Voltage VOUT ................. 0.8V to 0.9 x VIN Operating Temperature ............. -40C to +85C
Thermal Resistance
(3)
QFN10 (3mm x 3mm) ............. 50 ...... 12... C/W SOIC8E .................................. 50 ...... 10... C/W
Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1" square of 1 oz copper.
JA
JC
ELECTRICAL CHARACTERISTICS (4)
Parameters
VIN = VEN = 3.6V, VCC = 5V (MP2107A Only), TA = +25C, unless otherwise noted.
Supply Current Condition VEN = VIN VFB = 0.85V VEN = 0V, VIN = 6V Rising Edge Min
Typ 750 1
Max
Units A V mV
Shutdown Current IN Undervoltage Lockout Threshold IN Undervoltage Lockout Hysteresis Regulated FB Voltage FB Input Current EN High Threshold EN Low Threshold
A
2.59 210
2.69
TA = +25C VFB = 0.85V -40C TA +85C -40C TA +85C
0.776 1.6
0.800 50
0.824
0.4
V nA V V 2
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2009122006580007
MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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ELECTRICAL CHARACTERISTICS (4) (continued)
VIN = VEN = 3.6V, VCC = 5V (MP2107A Only), TA = +25C, unless otherwise noted.
Parameters Condition Internal Soft-Start Time High-Side Switch On-Resistance ISW = 300mA Low-Side Switch On-Resistance ISW = -300mA VEN = 0V; VIN = 5.5V SW Leakage Current VSW = 0V or 5.5V BS Under Voltage Lockout Threshold High-Side Switch Current Limit Sourcing Low-Side Switch Current Limit Sinking Oscillator Frequency Maximum Synch Frequency Minimum Synch Frequency Minimum On Time Maximum Duty Cycle POK Upper Trip Threshold FB respect to the nominal value POK Lower Trip Threshold FB respect to the nominal value POK Output Voltage Low ISINK = 5mA POK Deglitch Timer Thermal Shutdown Threshold Hysteresis = 20C Min Typ 120 80 60 Max Units s m m A V
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-10 10 1.8 1.2 6.5 3.5 1.5 2 1 50 90 10 -10 1.8 0.4 30 150 A A MHz MHz MHz ns % % % V s C
Note: 4) Production test at +25C. Specifications over the temperature range are guaranteed by design and characterization.
PIN FUNCTIONS
SOIC Pin# QFN Pin# - 6
Name POK IN
3
4, 7 3, 8
6, 7 2 4
SW
2, 9 5
GND BS
1
1
FB
8
10
EN/SYNC
5
-
VCC
Description Open Drain Power Good Output. "HIGH" output indicates VOUT is within 10% window. "LOW" output indicates VOUT is out of 10% window. POK is pulled down in shutdown. Input Supply. A decoupling capacitor to ground is required close to these pins to reduce switching spikes. Switch Node Connection to the Inductor. These pins connect to the internal high and low-side power MOSFET switches. All SW pins must be connected together externally. Ground. Connect these pins with larger copper areas to the negative terminals of the input and output capacitors. Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side gate driver. Feedback. This is the input to the error amplifier. An external resistive divider connects this pin between the output and GND. The voltage on the FB pin compares to the internal 0.8V reference to set the regulation voltage. Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock signal to this pin synchronizes the internal oscillator frequency to the external clock. Logic circuitry bias supply. Connect directly to VIN or 3.3V to 5V supply. Bypass with a low ESR 1F ceramic capacitor as close to the pin as possible
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - PHOTOFAST INTERNAL USE ONLY
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VCC = 5V (MP2107A Only), VO = 1.8V, L1 = 1.0H, C2 = 47F, TA = +25C, unless otherwise noted.
Steady State Operation
No Load
VOUT 10mV/div.
Steady State Operation
Half Load
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VOUT 10mV/div. I INDUCTOR 1A/div. I INDUCTOR 2A/div. VSW 5V/div. VSW 5V/div.
400ns/div.
400ns/div.
Steady State Operation
Full Load
Load Transient
1A-4A Step Resistive Load
VOUT 10mV/div.
VOUT 200mV/div.
I INDUCTOR 2A/div. VSW 5V/div.
I INDUCTOR 1A/div.
400ns/div.
Start-up through Enable
No Load
Start-up through Enable
Full Load
VOUT 1V/div.
VOUT 1V/div.
VPOK 2V/div.
VPOK 2V/div.
VEN 2V/div.
VEN 2V/div.
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - PHOTOFAST INTERNAL USE ONLY
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VCC = 5V (MP2107A Only), VO = 1.8V, L1 = 1.0H, C2 = 47F, TA = +25C, unless otherwise noted.
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No Load Full Load
VOUT 1V/div. VOUT 2V/div. VEN 2V/div. VEN 5V/div. VPOK 2V/div. VPOK 2V/div.
Shut-down through Enable
Shut-down through Enable
400ms/div.
1ms/div.
Short Circuit Protection
VIN =5V, VOUT =1.8V
Short Circuit Recovery
VIN =5V, VOUT =1.8V
VOUT 1V/div.
VOUT 1V/div.
Vsw 5V/div.
Vsw 5V/div.
I INDUCTOR 2A/div.
I INDUCTOR 2A/div.
1ms/div.
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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FUNCTIONAL BLOCK DIAGRAM
POK
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0.88V
+ --
IN IN
EN
0.72V
+ --
BS
EN/SYNC
EN/SYNC LOGIC
EN
EXCLK
LOGIC
CLK
PWM CURRENT COMPARATOR
OSC
SLOPE
0.5pF
1.2 MEG 17pF
FB
0.8V
-+ +
COMP
SLOPE COMPENSATION AND PEAK CURRENT LIMIT
SOFT -START
Figure 1--Functional Block Diagram (MP2107)
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+ --
SW SW
GND GND
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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FUNCTIONAL DESCRIPTION
PWM Control The MP2107 is a constant frequency peak-currentmode control PWM switching regulator. Refer to the functional block diagram. The high side N-Channel DMOS power switch turns on at the beginning of each clock cycle. The current in the inductor increases until the PWM current comparator trips to turn off the high side DMOS switch. The peak inductor current at which the current comparator shuts off the high side power switch is controlled by the COMP voltage at the output of feedback error amplifier. The transconductance from the COMP voltage to the output current is set at 11.25A/V.
This current-mode control greatly simplifies the feedback compensation design by approximating the switching converter as a single-pole system. Only Type II compensation network is needed, which is integrated into the MP2107. The loop bandwidth is adjusted by changing the upper resistor value of the resistor divider at the FB pin. The internal compensation in the MP2107 simplifies the compensation design, minimizes external component counts, and keeps the flexibility of external compensation for optimal stability and transient response.
low-side switches until the voltage on the internal soft-start capacitor exceeds the sensed output voltage at the FB pin.
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Power Good Output (POK PIN) The MP2107 includes an open-drain Power Good output that indicates whether the regulator output is within 10% of its nominal output. When the output voltage moves outside this range, the POK output is pulled to ground. There is a 30s deglitch time when the POK output change its state. Bootstrap (BST PIN) The gate driver for the high-side N-channel DMOS power switch is supplied by a bootstrap capacitor connected between the BS and SW pins. When the low-side switch is on, the capacitor is charged through an internal boost diode. When the high-side switch is off and the low-side switch turns on, the voltage on the bootstrap capacitor is boosted above the input voltage and the internal bootstrap diode prevents the capacitor from discharging. Enable and Frequency Synchronization (EN/SYNC PIN) This is a dual function input pin. Forcing this pin below 0.4V for longer than 4s shuts down the part; forcing this pin above 1.6V for longer than 4s turns on the part. Applying a 1MHz to 2MHz clock signal to this pin also synchronizes the internal oscillator frequency to the external clock. When the external clock is used, the part turns on after detecting the first few clocks regardless of duty cycles. If any ON or OFF period of the clock is longer than 4s, the signal will be intercepted as an enable input and disables the synchronization. Soft-Start and Output Pre-Bias Startup When the soft-start period starts, an internal current source begins charging an internal soft-start capacitor. During soft-start, the voltage on the softstart capacitor is connected to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the reference voltage of 0.8V. At this point the reference voltage takes over at the noninverting error amplifier input. The soft-start time is internally set at 120s. If the output of the MP2107 is pre-biased to a certain voltage during startup, the IC will disable the switching of both high-side and
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Over Current Protection The MP2107 offers cycle-to-cycle current limiting for both high-side and low-side switches. The high-side current limit is relatively constant regardless of duty cycles. When the output is shorted to ground, causing the output voltage to drop below 70% of its nominal output, the IC is shut down momentarily and begins discharging the soft start capacitor. It will restart with a full soft-start when the soft-start capacitor is fully discharged. This hiccup process is repeated until the fault is removed.
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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APPLICATION INFORMATION
Output Voltage Setting The external resistor divider sets the output voltage (see Page 1, Schematic Diagram). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation (refer to description function). The relation between R1 and feedback loop bandwidth (fC), output capacitance (CO) is as follows: 1.24 x 10 6 . R1(K) = fc(KHz ) x C O (F) The feedback loop bandwidth (fC) is no higher than 1/10th of switching frequency of MP2107. In the case of ceramic capacitor as CO, it is usually set in the range of 50KHz and 150KHz for optimal transient performance and good phase margin. If an electrolytic capacitor is used, the loop bandwidth is no higher than 1/4 of the ESR zero frequency (fESR). fESR is given by: 1 fESR = 2 x RESR x CO For example, choose fC=70KHz with a ceramic capacitor, CO=47F, R1 is estimated to be 400K. R2 is then given by:
R2 = R1 VOUT -1 0.8V
where IL is Inductor Ripple Current. Choose inductor ripple current approximately 30% of the maximum load current, 4A. The maximum inductor peak current is:
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IL(MAX) = ILOAD + IL 2
Under light load conditions, larger inductance is recommended for improved efficiency.
Input Capacitor Selection The input capacitor reduces the surge current drawn from the input and the switching noise from the device. The input capacitor impedance at the switching frequency shall be less than input source impedance to prevent high frequency switching current passing to the input source. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 47F capacitor is sufficient. Table 1--Resistor Selection vs. Output Voltage Setting
R1 R2 L Vout 1.2V 1.5V 1.8V 2.5V 3.3V Cout (Ceramic) 47F 47F 47F 47F 47F 400k 400k 400k 400k 400k 806k 453k 316k 187k 127k 0.47H-1H 0.47H-1H 0.47H-1H 0.47H-1H 0.47H-1H
Output Capacitor Selection The output capacitor keeps output voltage ripple small and ensures a stable regulation loop. The output capacitor impedance shall be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. If an electrolytic capacitor is used, pay attention to output ripple voltage, extra heating, and the selection of feedback resistor R1 (refer to "Output Voltage Setting" section) due to the large ESR of electrolytic capacitor. The output ripple VOUT is approximately:
VOUT
VOUTx(VIN - VOUT) 1 x(ESR + ) VINxfOSCxL 8xfOSCxC3
Inductor Selection A 0.47H to 1H inductor with DC current rating at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance shall be <10m. See Table 2 for recommended inductors and manufacturers. For most designs, the inductance value can be derived from the following equation: VOUTx(VIN - VOUT) L= VINxILxfOSC
External Schottky Diode For this part, an external schottky diode is recommended to be placed close to "SW" and "GND" pins, especially when the output current is larger than 2A. With the external schottky diode, the voltage spike and negative kick on "SW" pin can be minimized; moreover, the conversion efficiency can also be improved a little.
For the external schottky diode selection, it's noteworthy that the maximum reverse voltage rating of the external diode should be larger than
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - PHOTOFAST INTERNAL USE ONLY
the maximum input voltage. As for the current rating of this diode, 0.5A rating should be sufficient
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Table 2--Suggested Surface Mount Inductors
Inductance (H) 0.55 Max DCR (m) 4.5 Manufacturer Part Number Current Rating (A) 14 Dimensions L x W x H (mm3) 7x6.9x3 Wurth Electronics 744310055 744310095 0.95 1 7.4 11 11 7x6.9x3 TOKO B1015AS-1R0N 6.9 8.4x8.3x4
PC Board Layout PCB layout is very important to achieve stable operation. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines as follows. Here, the typical application circuit is taken as an example to illustrate the key layout rules should be followed. 1) For MP2107, a PCB layout with more than (or) four layers is recommended. 2) The high current paths (GND, IN and SW) should be placed very close to the device with short, direct and wide traces. 3) For MP2107, two input ceramic capacitors (2 x (10F~22F)) are strongly recommended to be placed on both sides of the MP2107 package and keep them as close as possible to the "IN"
and "GND" pins. If this placement is not possible, a ceramic cap (10F~47F) must be placed across PIN7-"IN"and PIN9-"GND" since the internal Vcc supply is powered from PIN7, and good decoupling is needed to avoid any interference issues. For MP2107A, a input ceramic capacitor should be placed as close as possible to "IN" and "GND" pins. 4) The external feedback resistors shall be placed next to the FB pin. Keep the FB trace as short as possible. Don't place test points on FB trace if possible. 5) Keep the switching node SW short and away from the feedback network. 6) For MP2107A, a RC low pass filter is recommended for VCC supply. The Vcc decoupling capacitor must be placed as close as possible to "VCC" pin and "GND" pin.
Recommended Layout Pattern
Top Layer
Inner Layer 1
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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Inner Layer 2 Bottom Layer Figure 2--Recommended PCB Layout of MP2107 Top Layer Bottom Layer Figure 3--Recommended PCB Layout of MP2107A
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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TYPICAL APPLICATION CIRCUIT
Vin 2.7V to 5.5V C1 10uF C2 10uF 6 4,7 IN BS POK 5 SW 3,8 C4 100nF
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R4 100k
L1 1uH
MP2107
10
R3 100k
EN/SYNC FB GND 2,9
1
D1 B0530
R1 400k
Vout 1.8V/4A
R2 316k
C3 47uF
Figure 4--Typical application circuit of MP2107
C4 100nF
Vin 2.7V to 5.5V
R3 10
C1 22uF
3
4
5
IN
BS
Vcc
SW
6,7
L1 1uH
C3 1uF
MP2107A
8
R4 100k
EN/SYNC GND 2
1
D1 B0530
Vout 1.8V/4A
FB
R1 400k
R2 316k
C2 47uF
Figure 5--Typical application circuit of MP2107A
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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PACKAGE INFORMATION
QFN10 (3mm x 3mm)
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PIN 1 ID MARKING PIN 1 ID SEE DETAIL A 0.18 0.30 10 1 PIN 1 ID INDEX AREA 2.90 3.10 0.50 BSC 2.25 2.55 6 5
2.90 3.10
0.30 0.50
1.45 1.75
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A R0.20 TYP.
PIN 1 ID OPTION B R0.20 TYP.
0.20 REF
0.80 1.00
0.00 0.05
SIDE VIEW
DETAIL A
2.90
NOTE:
0.70
1.70
0.25
1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5. 5) DRAWING IS NOT TO SCALE.
2.50
0.50
RECOMMENDED LAND PATTERN
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MP2107/MP2107A - 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
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PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80) 0.197(5.00) 0.124(3.15) 0.136(3.45)
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8 5 PIN 1 ID 0.150(3.80) 0.157(4.00) 0.228(5.80) 0.244(6.20) 0.089(2.26) 0.101(2.56) 1 4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.013(0.33) 0.020(0.51)
0.051(1.30) 0.067(1.70) SEATING PLANE 0.000(0.00) 0.006(0.15)
0.0075(0.19) 0.0098(0.25)
0.050(1.27) BSC
SIDE VIEW
FRONT VIEW
0.010(0.25) x 45o 0.020(0.50)
GAUGE PLANE 0.010(0.25) BSC
0.024(0.61) 0.063(1.60)
0.050(1.27)
0o-8o
0.016(0.41) 0.050(1.27)
DETAIL "A"
0.103(2.62)
0.213(5.40)
NOTE:
0.138(3.51)
RECOMMENDED LAND PATTERN
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA. 6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.
MP2107/MP2107A Rev. 0.92 www.MonolithicPower.com 8/11/2009 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved.
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2009122006580007

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